M16C1N Datasheet, PDF (67/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
10. Interrupt
10.1.5.6 Interrupt Response Time
'Interrupt response time' is the period between the instant an interrupt occurs and the instant the
first instruction within the interrupt routine has been executed. This time comprises the period from
the occurrence of an interrupt to the completion of the instruction under execution at that moment
(a) and the time required for executing the interrupt sequence (b). Figure 10.5 shows the interrupt
response time.
Interrupt request generated Interrupt request acknowledged
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
Time
Instruction in
interrupt routine
(a) A time from when an interrupt request is generated till when the instruction then executing is
completed. The length of this time varies with the instruction being executed. The DIVX instruction
requires the longest time, which is equal to 30 cycles (without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table below. Note, however, that
the values in this table must be increased 2 cycles for the DBC interrupt and 1 cycle for the address match and
single-step interrupts.
Locate an interrupt vector address in an even address, if possible.
Interrupt vector address Stack pointer (SP) value
Even
Even
Even
Odd
Odd
Even
Odd
Odd
Without wait
18 cycles
19 cycles
19 cycles
20 cycles
Figure 10.5 Interrupt response time
Rev.1.00 Oct 20, 2004 page 55 of 222
REJ09B0007-0100Z