M16C1N Datasheet, PDF (58/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
10. Interrupt
10.1.3 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.
10.1.3.1 Special Interrupts
Special interrupts are non-maskable interrupts.
• Reset
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Reset occurs if an "L" is input to the RESET pin.
• UART0 reception interrupt
UART0 reception interrupt occurs when UART0 is received. This interrupt can be enabled with bit
2 of the INT0 input filter select register (address 001E16).
This interrupt is exclusively for the debugger, do not use it in other circumstances.
_______
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Oscillation stop detection/watchdog timer interrupt
Generated by the oscillation stop detection or watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug
flag (D flag) set to "1", a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated
by the address match interrupt register is executed with the address match interrupt enable bit set
to "1".
If an address other than the first address of the instruction in the address match interrupt register is
set, no address match interrupt occurs.
10.1.3.2 Peripheral I/O Interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. The interrupt vector
______
table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses.
Peripheral I/O interrupts are maskable interrupts.
• CAN0 error interrupt
Tis is an interrupt that CAN error generates.
• CAN0 wake up interrupt
CAN0 wake up interrupt occurs if a falling edge is input to the CRx pin.
• CAN0 successful reception interrupt
This is an interrupt that the CAN reception generates.
• CAN0 successful transmission interrupt
This is an interrupt that the CAN transmission generates.
• Key-input interrupt
___
A key-input interrupt occurs if a falling or rising edge is input to the KI pin.
• A/D conversion interrupt
This is an interrupt that the A/D converter generates.
• UART0 and UART1 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0 and UART1 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer 1 interrupt
This is an interrupt that timer 1 generates.
Rev.1.00 Oct 20, 2004 page 46 of 222
REJ09B0007-0100Z