M16C1N Datasheet, PDF (165/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
16.12.2 Transmission
Figure 16.25 shows the timing of the transmit sequence.
16. CAN Module
SOF
CANbus
TrmReq
(1)
TrmActive
(1)
(2)
SentData
Succ. Xmit Int.
TrmState
TrmSucc
(1)
(2)
MBOX
i=0 to15
Figure 16.25 Timing of Transmit Sequence
ACK
EOF
IFS SOF
B(4)
(3)
(3)
(3)
Transmission slot No.
(1) If the TrmReq bit of the C0MCTLi register (i=0 to 15) is set to "1" (Transmission slot) in bus idle
state, the TrmActive bit of the C0MCTLi register and the TrmState bit of the C0STR register are set
to "1" (Transmitting/Transmitter), and the CAN module starts transmitting.
(2) If the arbitration is lost after the CAN module starts transmitting, the TrmActive and TrmState bits
are set to "0".
(3) If the transmission is successful without lost arbitration, the SentData bit of the C0MCTLi register is
set to "1" (Transmission is successfully completed) and TrmActive bit of the C0MCTLj register is
set to "0" (Waiting for bus idle or completion of arbitration). And when the interrupt enable bits of
the C0ICR register = 1 (Interrupt enabled), CAN0 successful transmission interrupt request is gen-
erated and the MBOX (the slot number which transmitted the message) and TrmSucc bits of the
C0STR register are changed.
(4) When starting the next transmission, set the SentData and TrmReq bits to "0", then set the TrmReq
bit to "1" after checking that the SentData and TrmReq bits are set to "0".
Rev.1.00 Oct 20, 2004 page 153 of 222
REJ09B0007-0100Z