M16C1N Datasheet, PDF (76/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
10. Interrupt
10.5 Key Input Interrupt
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When the direction register of any of P10 to P13 is set for input and the KIi (i=0 to 3) input enable bit of this
port is set for enabled, if a falling or rising edge is input to that port, a key input interrupt is generated. A
key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop
mode.
Figure 10.14 shows the block diagram of the key input interrupts. When the appropriate signal ("L" for a
pin that has falling edge selected and "H" for a pin that has rising edge selected) is input to a pin for the
input inhibit process has not been executed, inputs to the other pins are not detected as interrupts.
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You should overwrite the KIi (i=0 to 3) input polarity select bit or the KIi (i =0 to 3) input enable bit only
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under conditions where the key input interrupt is disabled. After overwriting the KIi (i=0 to 3) input polarity
_____
select bit or the KIi (i=0 to 3) input enable bit, clear the interrupt request bit, and then enable the key input
interrupt.
Pull-up
transistor
Port P10-P13
pull-up select bit
Port P13
direction register
KI3 input enable bit
Port P13
direction register
P13/KI3
P12/KI2
Pull-up
transistor
KI2 input enable bit
Port P12
direction register
Pull-up
transistor
KI1 input enable bit
Port P11
direction register
KI3 input polarity
select bit
KI2 input
polarity
select bit
P11/KI1
P10/KI0
Pull-up
transistor
KI0 input enable bit
Port P10
direction register
KI1 input
polarity
select bit
KI0 input
polarity
select bit
Figure 10.14 Block diagram of key input interrupt
Key input interrupt control register (address 004D16)
Interrupt control
circuit
Key input interrupt
request
Key input enable register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
KIEN
Address
009816
When reset
0016
Bit symbol
Bit name
Function
RW
KI0EN KI0 input enable bit
0 : Disabled
1 : Enabled
RW
KI0PL KI0 input polarity select bit
0 : Falling edge
1 : Rising edges
RW
KI1EN KI1 input enable bit
0 : Disabled
1 : Enabled
RW
KI1PL KI1 input polarity select bit
0 : Falling edge
1 : Rising edges
RW
KI2EN KI2 input enable bit
0 : Disabled
1 : Enabled
RW
KI2PL KI2 input polarity select bit
0 : Falling edge
1 : Rising edges
RW
KI3EN KI3 input enable bit
0 : Disabled
1 : Enabled
RW
KI3PL KI3 input polarity select bit
0 : Falling edge
1 : Rising edges
RW
Figure 10.15 Key input enable register
Rev.1.00 Oct 20, 2004 page 64 of 222
REJ09B0007-0100Z