M16C1N Datasheet, PDF (123/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
13. Serial I/O
UARTi transmit/receive mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
UiMR(i=0,1)
Address
00A016, 00A816
When reset
0016
Bit
symbol
Bit name
Function
(During clock synchronous serial I/O mode)
Function
(During UART mode)
RW
SMD0
SMD1
Serial I/O mode select bit
Must be fixed to 001
b2 b1 b0
0 0 0 : Serial I/O invalid
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
SMD2
b2 b1 b0
1 0 0 : Transfer data 7 bits long _RW
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
RW
0 1 0 : Inhibited
0 1 1 : Inhibited
1 1 1 : Inhibited
RW
CKDIR Internal/external clock
select bit
0 : Internal clock
0 : Internal clock
1 : External clock (Note 1) 1 : External clock
RW
STPS Stop bit length select bit Invalid
PRY Odd/even parity select bit Invalid
PRYE Parity enable bit
Invalid
0 : One stop bit
1 : Two stop bits
RW
Valid when bit 6 = "1"
0 : Odd parity
RW
1 : Even parity
0 : Parity disabled
1 : Parity enabled
RW
Reserved bit
Set to "0"
RW
Note 1: Set the corresponding port direction register to "0".
UARTi transmit/receive control register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
UiC0(i=0,1)
Address
00A416, 00AC16
When reset
0816
Bit
symbol
Bit name
Function
(During clock synchronous serial I/O mode)
Function
(During UART mode)
RW
b1 b0
b1 b0
CLK0 BRG count source
0 0 : f1 is selected
0 0 : f1 is selected
RW
select bit
0 1 : f8 is selected
0 1 : f8 is selected
CLK1
1 0 : f32 is selected
1 0 : f32 is selected
1 1 : fc is selected
1 1 : fc is selected
RW
Reserved bit
Set to "0"
RW
TXEPT Transmit register empty 0 : Data present in transmit
0 : Data present in transmit register
flag
register (during transmission) (during transmission)
1 : No data present in transmit 1 : No data present in transmit
RO
register (transmission
register (transmission completed)
completed)
Nothing is assigned
In an attempt to write to this bit, write "0".
The value, if read, turn out to be "0".
NCH Data output select bit 0 : TXDi pin is CMOS output 0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel 1 : TXDi pin is N-channel open- RW
open-drain output
drain output
CKPOL CLK polarity select bit 0 : Transmit data is output Set to "0"
at falling edge of transfer
clock and receive data is
input at rising edge
1 : Transmit data is output
RW
at rising edge of transfer
clock and receive data is
input at falling edge
UFORM Transfer format select bit 0 : LSB first
1 : MSB first
Set to "0"
RW
Figure 13.4 Serial I/O-related registers (2)
Rev.1.00 Oct 20, 2004 page 111 of 222
REJ09B0007-0100Z