M16C1N Datasheet, PDF (127/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
13. Serial I/O
• Example of transmit timing (when internal clock is selected)
Tc
Transfer clock
"1"
Transmit enable
bit (TE)
"0"
Transmit buffer ^"1"
empty flag (Tl) _"0"
CLKi
Data is set in UARTi transmit buffer
register
TCLK
Transferred from UARTi transmit buffer register to UARTi transmit
register
Stopped pulsing because transfer enable bit = "0"
TxDi
Transmit
"1"
register empty
flag (TXEPT)
"0"
Transmit interrupt ^"1"
request bit (IR) "0"
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
Internal clock is selected.
CLK polarity select bit = 0.
Transmit interrupt cause select bit = 0.
Tc = TCLK = 2(n + 1) / fi
fi: frequency of BRGi count source (f1, f8, f32, fc)
n: value set to BRGi
• Example of receive timing (when external clock is selected)
"1"
Receive enable
bit (RE)
"0"
"1"
Transmit enable
bit (TE)
"0"
Transmit buffer
"1"
empty flag (Tl)
"0"
Dummy data is set in UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
1 / fEXT
CLKi
Receive data is taken in
RxDi
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5
Receive complete
flag (Rl)
Transferred from UARTi receive register
"1"
to UARTi receive buffer register
"0"
Read out from UARTi receive buffer register
Receive interrupt ^"1"
request bit (IR)
"0"
Cleared to "0" when interrupt request is accepted, or cleared by software
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
External clock is selected.
CLK polarity select bit = 0.
fEXT: frequency of external clock
Meet the following conditions when the CLKi input level
before data reception = "H"
Transmit enable bit "1"
Receive enable bit "1"
Dummy data write to UARTi transmit buffer register
Figure 13.7 Typical transmit/receive timings in clock synchronous serial I/O mode
Rev.1.00 Oct 20, 2004 page 115 of 222
REJ09B0007-0100Z