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M16C1N Datasheet, PDF (53/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES
M16C/1N Group
8. Processor Mode
8. Processor Mode
8.1 Types of Processor Mode
The processor mode is single-chip mode. Table 8.1 lists features of processor mode.
Figure 8.1 shows the processor mode register 0 and 1.
Table 8.1 Features of processor mode
Processor mode
Access space
Pins to which I/O ports are assigned
Single chip mode SFR, Internal RAM, Internal ROM All pins are I/O ports or peripheral function I/O pins.
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
00
Symbol
PM0
Address
000416
When reset
XXXX0X002
Bit symbol
Bit name
Function
RW
Reserved bit
Set to "0"
RW
Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be
indeterminate.
PM03
Software reset bit
The device is reset when this bit
is set to "1". The value of this bit RW
is "0" when read.
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.
Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
PM1
Address
000516
When reset
00XXX0X02
Bit symbol
Bit name
Function
RW
PM10
DATAROM area access
bit (Note 2)
0 : Disabled
1 : Enabled
RW
Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be
indeterminate.
PM12
WDT interrupt/reset
switching bit
0 : Watchdog timer interrupt
1 : Reset (Note 3)
RW
Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.
Reserved bit
Set to "0"
RW
PM17
Wait bit
0 : No wait
1 : Wait
RW
Note 1: Set bit 1 of the protect register (address 000A16) to "1" when writing new values to this register.
Note 2: This bit is valid for the flash memory version. For the mask ROM version, this bit must be set to "0".
Note 3: After setting this bit to "1", can not change to "0" by software.
Figure 8.1 Processor mode register 0 and 1
Rev.1.00 Oct 20, 2004 page 41 of 222
REJ09B0007-0100Z