M16C1N Datasheet, PDF (134/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
14. A/D Converter
14. A/D Converter
The A/D converter consists of one 10-bit successive approximation A/D converter circuit with a capacitive
coupling amplifier. Pins P00 to P07, P10 to P13, P40 and P41 also function as the analog signal input pins.
The direction registers of these pins for A/D conversion must therefore be set to input. The Vref connect bit
(bit 5 at address 00D716) can be used to isolate the resistance ladder of the A/D converter from the refer-
ence voltage input pin (VREF) when the A/D converter is not used. Doing so stops any current flowing into
the resistance ladder from VREF, reducing the power dissipation. When using the A/D converter, start A/D
conversion only after connecting to VREF.
The result of A/D conversion is stored in the A/D registers. When set to 10-bit precision, the low 8 bits are
stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low
8 bits are stored in the even addresses.
Table 14.1 shows the performance of the A/D converter. Figure 14.1 shows the block diagram of the A/D
converter, and Figures 14.2 and 14.3 show the A/D converter-related registers.
Table 14.1 Performance of A/D converter
Item
Performance
Method of A/D conversion Successive approximation (capacitive coupling amplifier)
Analog input voltage (Note 1) 0V to VCC
Operating clock ØAD (Note 2) VCC = 5V fAD, divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN)
Resolution
8-bit or 10-bit (selectable)
Absolute precision
VCC = 5V • Without sample and hold function
±3LSB
• With sample and hold function (8-bit resolution)
±2LSB
• With sample and hold function (10-bit resolution)
AN0 to AN11 input: ±3LSB
ANEX0 and ANEX1 input (including mode in which external
operation amp is connected): ±7LSB
Operating modes
One-shot mode and repeat mode (Note 3)
Analog input pins
12 pins (AN0 to AN11) + 2 pins (ANEX0 to ANEX1)
A/D conversion start condition • Software trigger
A/D conversion starts when the A/D conversion start flag changes to "1"
Conversion speed per pin • Without sample and hold function
8-bit resolution: 49 ØAD cycles, 10-bit resolution: 59 ØAD cycles
• With sample and hold function
8-bit resolution: 28 ØAD cycles, 10-bit resolution: 33 ØAD cycles
Note 1: Does not depend on use of sample and hold function.
Note 2: Divide fAD if (XIN) exceeds 10MHz, and make ØAD equal to or lower than 10MHz. Also if Vcc is less
than 4.2V, divide fAD and make ØAD equal to or lower than fAD/2.
Without sample and hold function, set the ØAD frequency to 250kHz min.
With the sample and hold function, set the ØAD frequency to 1MHz min.
Note 3: In repeat mode, only 8-bit mode can be used.
Rev.1.00 Oct 20, 2004 page 122 of 222
REJ09B0007-0100Z