M16C1N Datasheet, PDF (87/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
12. Timers
12.2.1 Timer Mode
In this mode, the timer counts an internally generated count source.
(See Table 12.3) Figure 12.6 shows the Timer X mode register in timer mode.
Table 12.3 Specifications of timer mode
Item
Specification
Count source
Count operation
f1, f8, f32, fC32
• Down count
• When the timer underflows, it reloads the reload register contents before continuing
Divide ratio
counting
1
(n+1) X (m+1)
n: Set value of Prescaler X, m: Set value of Timer X
Count start condition
Count start flag is set (=1)
Count stop condition
Count start flag is reset (=0)
Interrupt request generation timing When Timer X underflows [Timer X interruption]
CNTR0 pin function
TXOUT pin function
Read from timer
Programmable I/O port or CNTR0 interrupt input pin
Programmable I/O port
Count value can be read out by reading Timer X register.
Same applies to Prescaler X register.
Write to timer
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
00
Symbol
TXMR
Address
008B16
When reset
0016
Bit symbol
Bit name
Function
RW
TXMOD0 Operation mode
b1 b0
0 0 : Timer mode
RW
select bit 0, 1
TXMOD1
(Note 1)
RW
R0EDG
CNTR0 polarity
0 : Rising edge
switching bit (Note 1) 1 : Falling edge
RW
TXS
Timer X count
start flag
0 : Stops counting
1 : Starts counting
RW
TXOCNT P30/TXOUT
select bit
0 : In timer mode, set to "0"
RW
TXMOD2 Operation mode
select bit 2
0 : In timer mode, set to "0"
RW
TXEDG
Effectual edge
reception flag
Invalid in timer mode.
When write, set "0". When read, this contents RW
is indeterminate.
TXUND
Timer X under
flow flag
Invalid in timer mode.
When write, set "0". When read, this contents RW
is indeterminate.
Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt. When using the interrupt, the interrupt must be enabled
after clearing the CNTR0 interrupt request bit to "0" using a MOV instruction.
Figure 12.6 Timer X mode register in timer mode
Rev.1.00 Oct 20, 2004 page 75 of 222
REJ09B0007-0100Z