M16C1N Datasheet, PDF (153/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
16.4.7 C0CONR Register
Figure 16.12 shows the C0CONR register.
16. CAN Module
CAN0 configuration register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C0CONR
Address
023A16
After reset
Indeterminate
Bit symbol
Bit name
Function
RW
BRP
Prescaler division ^{b3 b2 b1 b0}
ratio select bits
0 0 0 0 : Divide-by-1 of fCAN
0 0 0 1 : Divide-by-2 of fCAN
0 0 1 0 : Divide-by-3 of fCAN
RW
(Note 1)
1 1 1 0 : Divide-by-15 of fCAN
1 1 1 1 : Divide-by-16 of fCAN
SAM
Sampling control
bit
0 : One time sampling
1 : Three times sampling
RW
PTS
Propagation time
b7 b6 b5
segment control bits ^{0 0 0 : 1Tq}
0 0 1 : 2Tq
0 1 0 : 2Tq
RW
1 1 0 : 7Tq
1 1 1 : 8Tq
Note 1: fCAN serves for the CAN clock. The period is decided by configuration of the CCLKi bits (i = 4 to 6).
(b15)
(b8)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
C0CONR
Address
023B16
After reset
Indeterminate
Bit symbol
Bit name
Function
RW
PBS1
Phase buffer
b2 b1b0
segment 1
0 0 0 : Inhibited
control bits
0 0 1 : 2Tq
0 1 0 : 3Tq
RW
1 1 0 : 7Tq
1 1 1 : 8Tq
PBS2
Phase buffer
b5 b4 b3
segment 2
0 0 0 : Inhibited
control bits
0 0 1 : 2Tq
0 1 0 : 3Tq
RW
1 1 0 : 7Tq
1 1 1 : 8Tq
SJW
Re synchronization b7 b6
jump width
0 0 : 1Tq
control bits
0 1 : 2Tq
RW
1 0 : 3Tq
1 1 : 4Tq
Figure 16.12 C0CONR Register
Rev.1.00 Oct 20, 2004 page 141 of 222
REJ09B0007-0100Z