M16C1N Datasheet, PDF (47/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
6. Clock Generation Circuit
Transition of normal operation mode
CM06="1"
Main clock is oscillating
Sub clock is stopped
Medium-speed mode (divided-by-8 mode)
BCLK: f(XIN)/8
CM07="0" CM06="1"
CM22="0"
CM04="0"
CM04="1"
(Notes 1, 3)
CM22="1"
CM22="0" (Note 1)
Main clock is oscillating
Sub clock is stopped
On-chip oscillator mode (divided-by-8 mode)
BCLK: f(RING)/8
CM07="0" CM06="1"
CM05="0"
CM22="1"
Main clock is stopped
Sub clock is stopped _{CM05 = "0"}
On-chip oscillator mode
CM05 = "1"
CM07="0" (Note 1)
CM06="1"
CM04="0"
8-division mode
BCLK: f(RING)/8
CM07="0" CM06="1"
CM05="1"
CM22="1"
1-division mode (Note 3)
BCLK: f(RING)
CM07="0" CM06="0"
CM05="1" CM22="1"
CM16="0" CM17="0"
2-division mode (Note 3)
BCLK: f(RING)/2
CM07="0" CM06="0"
CM05="1" CM22="1"
CM16="1" CM17="0"
4-division mode (Note 3)
BCLK: f(RING)/4
CM07="0" CM06="0"
CM05="1" CM22="1"
CM16="0" CM17="1"
16-division mode (Note 3)
BCLK: f(RING)/16
CM07="0" CM06="0"
CM05="1" CM22="1"
CM16="1" CM17="1"
Main clock is oscillating
Sub clock is oscillating
High-speed mode
BCLK : f(XIN)
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "0"
Medium-speed mode
(divided-by-4 mode)
BCLK : f(XIN)/4
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "0"
Medium-speed mode
(divided-by-2 mode)
BCLK : f(XIN)/2
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "1"
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/16
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "1"
Medium-speed mode
(divided-by-8 mode)
CM07 = "0"
(Notes 1, 3)
BCLK : f(XIN)/8
CM07 = "0"
CM06 = "1"
CM07 = "1"
CM06 = "1"
(Note 2, 5)
Main clock is oscillating
Sub clock is oscillating
Low-speed mode
BCLK : f(XCIN)
CM07 = "1"
CM06 = "1"
CM06 = "0"
(Notes 1, 3)
CM04 = "0"
CM04 = "1"
Main clock is oscillating
Sub clock is stopped
High-speed mode
Medium-speed mod
(divided-by-2 mode)
BCLK : f(XIN)
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "0"
BCLK : f(XIN)/2
CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "1"
Medium-speed mode
(divided-by-4 mode)
Medium-speed mode
(divided-by-16 mode)
BCLK : f(XIN)/4
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "0"
BCLK : f(XIN)/16
CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "1"
CM07 = "0" (Note 1)
CM06 = "0" (Note 3)
CM04 = "1"
CM05 = "0"
CM05 = "1"
Main clock is stopped
Sub clock is oscillating
Low power dissipation mode
BCLK : f(XCIN)
CM07 = "1"
CM06 = "1"
Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM17 and CM16 before changing CM06.
Note 4: Transit in accordance with arrow.
Note 5: Before switching BCLK to other from the main clock, divide the main clock by 8 for
safety purposes to switch BCLK to the main clock again.
Figure 6.9 State transition in normal operation mode
Rev.1.00 Oct 20, 2004 page 35 of 222
REJ09B0007-0100Z