M16C1N Datasheet, PDF (190/238 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/10 SERIES

M16C/1N Group
19. Flash Memory Version
19.5 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten by executing software commands from the
CPU. Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-
board without having to use a ROM programmer, etc.
Make sure the program and the block erase commands are executed only on each block in the user ROM area.
When generating an interrupt request during erasure operation in CPU mode, the M16C/1N Group flash
memory can offer the erasure-suspend feature which allows erasure operation to be suspended and to
process the interrupt. User ROM area can be read in a program during erasure-suspend.
During CPU rewrite mode, the user ROM area be operated on in either Erase Write 0 (EW0) mode or
Erase Write 1 (EW1) mode. Table 19.3 lists the differences between Erase Write 0 (EW0) and Erase
Write 1 (EW1) modes.
Table 19.3 Differences between EW0 mode and EW1 mode
Item
EW0 mode
EW1 mode
Operation mode
• Single chip mode
Single chip mode
Areas in which a
• User ROM area
User ROM area
rewrite control
program can be located
Areas in which a
Must be transferred to any area other Can be executed directly in the user
rewrite control
than the flash memory (e.g., RAM) ROM area
program can be executed before being executed
Areas which can be
User ROM area (Note 1)
User ROM area (Note 1)
rewritten
However, this does not include the area
in which a rewrite control program
exists
Software command
None
• Program, Block Erase command
limitations
Cannot be executed on any block in
which a rewrite control program exists
• Read Status Register command
Cannot be executed
Modes after Program or Read Status Register mode
Read Array mode
Erase
CPU status during Auto Operating
Hold state (I/O ports retain the state in
Write and Auto Erase
which they were before the command
was executed)(Note 2)
Flash memory status • Read the FMR0 register's FMR00, Read the FMR0 register's FMR00,
detection
FMR06, and FMR07 bits in a
FMR06, and FMR07 bits in a program
program
• Execute the Read Status Register
command to read the status
register's SR7, SR5, and SR4 flags.
The shift conditions to Set the FMR4 register's FMR40 and The FMR register's FMR40 bit is "1" and
erasure-suspend (Note 3) RMR41 bits to "1" by program.
generated the interrupt request of
enabled interrupt.
Note 1: Can be rewritten block 0 and 1 when setting the FMR0 register's FMR02 bit to "1" and the FMR1 register's
FMR16 bit to "1". Block 2 and 3 can be rewriting by setting the FMR1 register's FMR16 bit to "1".
Note 2: Make sure no interrupts will occur.
Note 3: The conditions are met and it takes a maximum of td(SR-ES) time until a flash memory can be
read after shifting to erasure-suspend.
Rev.1.00 Oct 20, 2004 page 178 of 222
REJ09B0007-0100Z