MC68HC05L28 Datasheet, PDF (98/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

AD0
AD1
VRH
(VRH+VRL)/2
VRL
8-bit capacitive DAC
with sample and hold
VRH
VRL
Successive approximation
register and control
Result
A/D status/control register (ADSTAT)
CH0 CH1 CH2 CH3
ADON ADRC COCO
A/D result data register (ADDATA)
Figure 9-1 A/D converter block diagram
9
The result of each successive comparison is stored in the SAR and, when the conversion is
complete, the contents of the SAR are transferred to the read-only result data register ($17), and
the conversion complete flag, COCO, is set in the A/D status/control register ($15).
Note:
Any write to the A/D status/control register will abort the current conversion, reset the
conversion complete flag and start a new conversion on the selected channel.
At power-on or external reset, both the ADRC and ADON bits are cleared, thus the A/D is disabled.
MOTOROLA
9-2
A/D CONVERTER
TPG
MC68HC05L28