MC68HC05L28 Datasheet, PDF (62/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

6.2.1.2 Timer control register 2 (TCR2)
Timer control 2 (TCR2)
Address bit 7
$002D 0
bit 6 bit 5
0 OC2IE
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
0 CO2E 0
0 OLVL2 0000 0000
OC2IE — Output compare 2 interrupt enable
1 (set) – Output compare 2 interrupt enabled.
0 (clear) – Output compare 2 interrupt disabled.
CO2E — Timer compare 2 output enable
1 (set) – Output of timer compare 2 is enabled.
0 (clear) – Output of timer compare 2 is disabled.
6
Reset clears this bit.
OLVL2 — Output level 2
This bit determines the level that is clocked into the output level register by the next successful
output compare 2 and which will appear on the TCMP2 pin.
1 (set) – A high output level will appear on the TCMP2 pin.
0 (clear) – A low output level will appear on the TCMP2 pin.
When OLVL2 is set, a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level
that will appear on the TCMP2 pin.
Bits 1, 2 4, 6 and 7 — unused; always read 0.
MOTOROLA
6-6
16-BIT PROGRAMMABLE TIMER
TPG
MC68HC05L28