MC68HC05L28 Datasheet, PDF (117/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

Table 11-5 Read/modify/write instructions
Inherent
(A)
Addressing modes
Inherent
(X)
Direct
Indexed
(no
offset)
Indexed
(8-bit
offset)
Function
Increment
Decrement
Clear
Complement
Negate (two’s complement)
Rotate left through carry
Rotate right through carry
Logical shift left
Logical shift right
Arithmetic shift right
Test for negative or zero
Multiply
INC 4C 1 3 5C 1 3 3C 2 5 7C 1 5 6C 2 6
DEC 4A 1 3 5A 1 3 3A 2 5 7A 1 5 6A 2 6
CLR 4F 1 3 5F 1 3 3F 2 5 7F 1 5 6F 2 6
COM 43 1 3 53 1 3 33 2 5 73 1 5 63 2 6
NEG 40 1 3 50 1 3 30 2 5 70 1 5 60 2 6
ROL 49 1 3 59 1 3 39 2 5 79 1 5 69 2 6
ROR 46 1 3 56 1 3 36 2 5 76 1 5 66 2 6
LSL 48 1 3 58 1 3 38 2 5 78 1 5 68 2 6
LSR 44 1 3 54 1 3 34 2 5 74 1 5 64 2 6
ASR 47 1 3 57 1 3 37 2 5 77 1 5 67 2 6
TST 4D 1 3 5D 1 3 3D 2 4 7D 1 4 6D 2 5
MUL 42 1 11
Table 11-6 Control instructions
Function
Transfer A to X
Transfer X to A
Set carry bit
Clear carry bit
Set interrupt mask bit
Clear interrupt mask bit
Software interrupt
Return from subroutine
Return from interrupt
Reset stack pointer
No-operation
Stop
Wait
Mnemonic
TAX
TXA
SEC
CLC
SEI
CLI
SWI
RTS
RTI
RSP
NOP
STOP
WAIT
Inherent addressing mode
Opcode # Bytes # Cycles
97
1
2
9F
1
2
99
1
2
98
1
2
9B
1
2
9A
1
2
83
1
10
81
1
6
80
1
9
9C
1
2
9D
1
2
8E
1
2
8F
1
2
11
MC68HC05L28
CPU CORE AND INSTRUCTION SET
TPG
MOTOROLA
11-7