MC68HC05L28 Datasheet, PDF (67/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

6.2.4 Output compare registers
‘Output compare’ is a technique that may be used, for example, to generate an output waveform,
or to signal when a specific time period has elapsed, by presetting the output compare register to
the appropriate value. There are two output compare registers – OC1 and OC2. All the bits are
readable and writable and are not altered by the timer hardware or reset. If the compare function
is not needed, the two bytes of the output compare register can be used as storage locations.
6.2.4.1 Output compare register 1
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Output compare high 1 (OCH1) $0022
Unaffected
Output compare low 1 (OCL1) $0023
Unaffected
6
The 16-bit output compare register 1 is made up of two 8-bit registers at locations $22 (MSB) and
$23 (LSB). The contents of the output compare 1 register are compared with the contents of the
free-running counter once every four internal processor clock cycles. If a match is found, the output
compare 1 flag (OC1F) in the timer status register is set and the output level 1 (OLVL1) bit is
clocked to the TCMP1 pin. The output compare 1 register values and the output level 1 bit should
be changed after each successful comparison to establish a new elapsed timeout. An interrupt can
also accompany a successful output compare provided the corresponding interrupt enable bit
(OC1IE) is set.
After a processor write cycle to the output compare register 1 containing the MSB ($22), the output
compare function is inhibited until the LSB ($23) is also written. The user must write both bytes
(locations) if the MSB is written first. A write made only to the LSB will not inhibit the compare
function.
The processor can write to either byte of the output compare register 1 without affecting the other
byte. The output level 1 bit (OLVL1) is clocked to the output level 1 register whether the output
compare 1 flag (OC1F) is set or clear. The minimum time required to update the output compare 1
register is a function of the program rather than the internal hardware. Because the output
compare 1 flag and the output compare 1 register are not defined at power on, and not affected by
reset, care must be taken when initialising output compare functions with software. The following
procedure is recommended:
1) write to output compare high 1 to inhibit further compares;
2) read the timer status register to clear OC1F (if set);
3) write to output compare low 1 to enable the output compare 1 function.
MC68HC05L28
16-BIT PROGRAMMABLE TIMER
TPG
MOTOROLA
6-11