MC68HC05L28 Datasheet, PDF (104/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

10.1.3 Computer operating properly (COP) reset
The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a
specific time by a program reset sequence.
Note: COP timeout is prevented by periodically writing a ‘0’ to bit 0 of address $3FF0.
If the COP watchdog timer is allowed to timeout, an internal reset is generated to reset the MCU.
Because the internal reset signal is used, the MCU comes out of a COP reset in the same
operating mode it was in when the COP timeout was generated.
The COP reset function is enabled or disabled by a bit in the option register.
See Section 5.2 for more information on the COP watchdog timer.
10.2
Interrupts
10
The MCU can be interrupted by different sources – six maskable hardware interrupts and one
non-maskable software interrupt:
• External signal on the IRQ pins (IRQ0, IRQ1, IRQ2)
• Core timer
• 16-bit programmable timer
• I²C
• Software Interrupt Instruction (SWI)
Interrupts cause the processor to save the register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. The RTI instruction (return from interrupt) causes the
register contents to be recovered from the stack and normal processing to resume.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete. The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) and the
corresponding interrupt enable bit is set, the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
Table 10-1 shows the relative priority of all the possible interrupt sources. Figure 10-1 shows the
interrupt processing flow.
MOTOROLA
10-2
RESETS AND INTERRUPTS
TPG
MC68HC05L28