MC68HC05L28 Datasheet, PDF(105/156 Page) Motorola, Inc – Flexible general-purpose microcomputer

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MC68HC05L28 Datasheet, PDF (105/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

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Table 10-1 Interrupt priorities

Source

Reset

Software interrupt (SWI)

External interrupt (IRQ)

Core timer

I2C

Programmable timer

IRQx

CTCSR

MSR

TSR

Flags

IRQxINT

CTOF, RTIF

MIF

ICF, OCF, TOF

Vector Address

$3FFE, $3FFF

$3FFC, $3FFD

$3FFA, $3FFB

$3FF8, $3FF9

$3FF6, $3FF7

$3FF4, $3FF5

Priority

highest

lowest

10.2.1 Non-maskable software interrupt (SWI)

The software interrupt (SWI) is an executable instruction and a non-maskable interrupt: it is

executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI

is executed after interrupts that were pending when the SWI was fetched, but before interrupts

generated after the SWI was fetched. The SWI interrupt service routine address is speciï¬ed by the

contents of memory locations $3FFC and $3FFD.

10.2.2 Maskable hardware interrupts

If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are

masked. Clearing the I-bit allows interrupt processing to occur.

Note:

The internal interrupt latch is cleared in the ï¬rst part of the interrupt service routine;

therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit

is cleared.

MC68HC05L28

RESETS AND INTERRUPTS

TPG

MOTOROLA

10-3

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