MC68HC05L28 Datasheet, PDF (40/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

3.4.1.3 LATCH — EEPROM latch control
1 (set) – The EEPROM address and data buses are configured for
programming. This causes the address and data buses to be latched
3
when a write to EEPROM is carried out. EEPROM cannot be read if
LATCH = 1.
0 (clear) – The EEPROM address and data buses are configured for normal
reads.
3.4.1.4 EERC — EEPROM RC oscillator control
1 (set)
– The EEPROM uses an internal RC oscillator instead of the CPU
clock. After setting, wait for time t_RCON to allow the RC oscillator to
stabilize. It should be set by the user when the internal bus frequency
falls below 1.5 MHz.
0 (clear) – The EEPROM uses the CPU clock.
3.4.1.5 EEPGM — EEPROM program control
1 (set)
– Programming power is connected to the EEPROM array. EEPGM
can only be set if LATCH is set and is automatically cleared when
LATCH = 0.
0 (clear) – Programming power is disconnected from the EEPROM array.
Note: LATCH and EEPGM cannot be set on the same write operation
3.4.2 EPROM programming register (PCR)
EPROM program (PCR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$001C
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3-4
MEMORY AND REGISTERS
TPG
MC68HC05L28