MC68HC05L28 Datasheet, PDF(107/156 Page) Motorola, Inc – Flexible general-purpose microcomputer

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MC68HC05L28 Datasheet, PDF (107/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

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10.2.2.1 External interrupt (IRQ0, IRQ1, IRQ2)

These external interrupt sources use the same interrupt vector ($3FFA, $3FFB)

IRQ0

If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are

disabled. Clearing the I-bit enables interrupts. The interrupt request is latched immediately

following the falling edge of IRQ0. It is then synchronized internally and serviced by the interrupt

service routine located at the address speciï¬ed by the contents of $3FFA and $3FFB.

Either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-only trigger can be

selected by bit-1 (IRQED) in the option register ($1D). When IRQED is cleared, the interrupt is

edge-and-level sensitive and when set the interrupt is edge sensitive. IRQED can be written to

once only after a power-on-reset or external reset. This bit is cleared after reset.

IRQ1

Address bit 7

IRQ1 status/control register (IRQ1) $000A

bit 6 bit 5

bit 4 bit 3

bit 2

bit 1

bit 0

State

on reset

IRQ1INT IRQ1ENA IRQ1LV IRQ1EDGIRQ1RSTIRQ1VAL ??00 0000

This interrupt can be enabled independently and different sensitivities can be deï¬ned: falling edge,

falling edge and low level, rising edge, rising edge and high level. The interrupt is enabled by

setting bit 4 (IRQ1ENA) of register $0A and is disabled by clearing it. The interrupt vector, $3FFA

and $3FFB, is shared with the other IRQ interrupts. Bit 5 of register $0A is an interrupt ï¬ag

(IRQ1INT) which distinguishes between the interrupts and is set when an interrupt occurs. The

interrupt is cleared by writing 1 to the IRQ1RST bit which always reads 0. The status of IRQ1 can

be monitored by reading the IRQ1VAL bit (bit 0 on the IRQ1 register).

IRQ1INT â IRQ1 interrupt ï¬ag

1 (set) â A valid IRQ1 interrupt has been generated.

0 (clear) â No valid IRQ1 interrupt has been generated.

IRQ1ENA â IRQ1 interrupt enable

1 (set) â IRQ1 interrupts are enabled.

0 (clear) â IRQ1 interrupts are disabled.

IRQ1LV, IRQ1EDG â IRQ1 interrupt sensitivity bits

These two bits are used to select the sensitivity of the IRQ1 interrupt trigger according to

Table 10-2.

MC68HC05L28

RESETS AND INTERRUPTS

TPG

MOTOROLA

10-5

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