MC68HC05L28 Datasheet, PDF (110/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

10.2.2.4 I²C interrupts
There is an interrupt flag and three status flags for the I²C that cause an I²C interrupt when set
and enabled. These interrupts will vector to the service routine located at the address specified by
the contents of memory locations $3FF6 and $3FF7.
10.2.3 Hardware controlled interrupt sequence
The following three functions (RESET, STOP, and WAIT) are not in the strictest sense interrupts.
However, they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in
Section 2-5 and Figure 2-6.
RESET:
A reset condition causes the program to vector to its starting address, which is
contained in memory locations $3FFE (MSB) and $3FFF (LSB). The I-bit in the
condition code register is also set, to disable maskable interrupts.
STOP:
The STOP instruction causes the oscillator to be turned off and the processor to
‘sleep’ until an external interrupt (IRQ) interrupt occurs, or the device is reset.
WAIT:
The WAIT instruction causes all processor clocks to stop, but leaves the core timer
clock running. This ‘rest’ state of the processor can be cleared by reset, an external
interrupt (IRQ), or a timer interrupt. There are no special WAIT vectors for these
interrupts.
10
MOTOROLA
10-8
RESETS AND INTERRUPTS
TPG
MC68HC05L28