MC68HC05L28 Datasheet, PDF (86/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

8.4 Registers
8.4.1
I²C-bus address register (MADR)
Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1
I²C-bus address register (MADR) $0010 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1
bit 0
State
on reset
0000 000u
ADR7 – ADR1 — Slave address bits
These bits define the slave address of the I²C-bus, and are used in slave mode in conjunction with
the MAAS bit in the MSR register (see Section 8.4.4). These bits can be read and written at any time.
Bit 0 — reserved by Motorola.
8.4.2
I²C-bus frequency divider register (FDR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
I²C-bus frequency divider register (FDR) $0011
MBC4 MBC3 MBC2 MBC1 MBC0 uuu0 0000
8
MBC4 – MBC0 — Clock rate select bits
These bits can be read and written at any time.
These bits are used to prescale the clock for bit rate selection. Due to the potential slow rise and
fall times of the SCL and SDA signals the bus signals are sampled at the prescaler frequency. This
sampling incurs an overhead of six clocks per SCL pulse. The serial bit clock frequency is equal
to the CPU clock divided by the divider shown in Table 8-1, plus the sampling overhead of six
clocks per cycle.
For a 4 MHz external crystal operation, the serial bit clock frequency of the I²C-bus ranges from
460 Hz to 90909 kHz.
MOTOROLA
8-6
I²C-BUS
TPG
MC68HC05L28