MC68HC05L28 Datasheet, PDF (55/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

5.3.2 Core timer counter register (CTCR)
Core timer counter (CTCR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0009
0000 0000
The core timer counter register is a read-only register, which contains the current value of the 8-bit
ripple counter at the beginning of the timer chain.
Reset clears this register.
5
5.4
Core timer during WAIT
The CPU clock halts during the WAIT mode, but the core timer remains active. If the interrupts are
enabled, then a CTIMER interrupt will cause the processor to exit the WAIT mode.
5.5
Core timer during STOP
The timer is cleared when going into STOP mode. When STOP is exited by an external interrupt
or an external reset, the internal oscillator will restart, followed by an internal processor
stabilization delay (t_PORL). The timer is then cleared and operation resumes.
MC68HC05L28
CORE TIMER
TPG
MOTOROLA
5-5