MC68HC05L28 Datasheet, PDF (90/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

8.4.5
I²C-bus data register (MDR)
I²C-bus data register (MDR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0014 TRXD7 TRXD6 TRXD5 TRXD4 TRXD3 TRXD2 TRXD1 TRXD0 Undefined
These bits can be read and written at any time.
In master transmit mode, a write to this register will cause the data in it to be sent to the bus
automatically, MSB first. In master receive mode, a read of this register initiates the transfer of the
next incoming byte of data into the register. See Figure 8-3.
In slave transmit mode, the SCL line is forced low until data is written into this register, to prevent
transmission. Similarly, in slave receive mode, the data bus must be read before a transmission
can occur.
8.5 Programming
8.5.1 Initialization
8
After a reset, the I²C-bus control register (MCR) is in a default state. Before the I²C-bus can be
used, it must be initialized as follows:
1) Configure the frequency divider register for the desired SCL frequency.
2) Configure the I²C-bus address register (MADR) to define the slave address
of the I²C-bus.
3) Set the MEN bit in the I²C-bus control register (MCR) to enable the I²C-bus
system.
4) Configure the other bits in the MCR register.
8.5.2 START signal and the first byte of data
After the initialization procedure has been completed, serial data can be transmitted by selecting
the ‘master transmitter’ mode. If the device is connected to a multi-master bus system, the state of
the I²C-bus busy bit (MBB) must be tested to check whether the serial bus is free. If the bus is free
(MBB = 0), the START condition and the first byte (the slave address) can be sent. An example of
a program that does this is shown below:
CHFLAG
SEI
BRSET
;DISABLE INTERRUPT
5,MSR,CHFLAG ;CHECK THE MBB BIT OF THE STATUS
;REGISTER. IF IT IS SET, WAIT
MOTOROLA
8-10
I²C-BUS
TPG
MC68HC05L28