MC68HC05L28 Datasheet, PDF (109/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

Table 10-3 IRQ2 interrupt sensitivity
IRQ2LV
0
0
1
1
IRQ2EDG
0
1
0
1
Interrupt sensitivity
Falling edge
Rising edge
Falling edge and low level
Rising edge and high level
IRQ2RST — IRQ2 reset
The IRQ2 interrupt is cleared by writing a ‘1’ to this bit. This bit is write-only and always returns
zero.
IRQ2VAL — IRQ2 pin status
The IRQ2VAL bit reflects current status of the IRQ2 pin.
10.2.2.2 Real time and core timer (CTIMER) interrupts
There are two core timer interrupt flags that cause a CTIMER interrupt whenever an interrupt is
enabled and its flag becomes set (RTIF and CTOF). The interrupt flags and enable bits are located
in the CTIMER control and status register (CTCSR). These interrupts vector to the same interrupt
service routine, whose start address is contained in memory locations $3FF8 and $3FF9 (see
Section 5.3.1 and Figure 5-1).
To make use of the real time interrupt the RTIE bit must first be set. The RTIF bit will then be set
after the specified number of counts.
To make use of the core timer overflow interrupt, the CTOFE bit must first be set. The CTOF bit will
then be set when the core timer counter register overflows from $FF to $00.
10
10.2.2.3 Programmable 16-bit timer interrupt
There are five interrupt flags that cause a timer interrupt when set and enabled. The timer interrupt
enable bits are located in the timer control registers (TCR) and the timer interrupt flags are located
in the timer status registers (TSR). All interrupts vector to the same service routine, whose start
address is contained in memory locations $3FF4 and $3FF5. In WAIT mode the CPU clock halts
but the timer continues to run.
MC68HC05L28
RESETS AND INTERRUPTS
TPG
MOTOROLA
10-7