MC68HC05L28 Datasheet, PDF (87/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

Table 8-1 I²C-bus prescaler
MCB4-0
00000
00001
00010
00011
00100
00101
00110
00111
Divider
22
24
28
34
44
48
56
68
MCB4-0 Divider
0 1 0 0 0 88
0 1 0 0 1 96
0 1 0 1 0 112
0 1 0 1 1 136
0 1 1 0 0 176
0 1 1 0 1 192
0 1 1 1 0 224
0 1 1 1 1 272
MCB4-0 Divider
1 0 0 0 0 352
1 0 0 0 1 384
1 0 0 1 0 448
1 0 0 1 1 544
1 0 1 0 0 704
1 0 1 0 1 768
1 0 1 1 0 896
1 0 1 1 1 1088
MCB4-0 Divider
1 1 0 0 0 1408
1 1 0 0 1 1536
1 1 0 1 0 1792
1 1 0 1 1 2176
1 1 1 0 0 2816
1 1 1 0 1 3072
1 1 1 1 0 3584
1 1 1 1 1 4352
8.4.3
I²C-bus control register (MCR)
These bits can be read and written at any time.
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
I²C-bus control register (MCR) $0012 MEN MIEN MSTA MTX TXAK
0000 0uuu
MEN — I²C-bus enable
8
1 (set) – I²C-bus interface system is enabled. This bit must be set before any
other MCR bits can be set.
0 (clear) –
I²C-bus interface system is disabled and reset. This is the power-on
reset case. When low, the interface is held in reset, but registers can
be accessed.
If the module is enabled in the middle of a byte transfer, the interface behaves as follows:
slave mode ignores the current transfer on the bus and starts operating when a subsequent start
condition is detected.
Master mode is not aware that the bus is busy, so if a start cycle is initiated the current bus cycle
may become corrupt. This results in either the current bus master or the I²C-bus losing arbitration,
after which bus operation returns to normal.
MIEN — I²C-bus interrupt enable
1 (set) – I²C-bus interrupt is requested when MIF is set.
0 (clear) – I²C-bus interrupt is disabled.
MC68HC05L28
I²C-BUS
TPG
MOTOROLA
8-7