MC68HC05L28 Datasheet, PDF (61/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

TOIE — Timer overflow interrupt enable
1 (set) – Timer overflow interrupt enabled.
0 (clear) – Timer overflow interrupt disabled.
CO1E — Timer compare 1 output enable
1 (set) – Output of timer compare 1 is enabled.
0 (clear) – Output of timer compare 1 is disabled.
Reset clears this bit.
IEDG1 — Input edge 1
This bit determines which level transition on TCAP1 pin will trigger the transfer of the free-running
counter to input capture register.
1 (set) – TCAP1 is rising edge sensitive.
6
0 (clear) – TCAP1 is falling edge sensitive.
When IEDG1 is set, a rising edge on the TCAP1 pin will trigger a transfer of the free-running counter
value to the input capture register. When clear, a falling edge triggers the transfer.
Reset does not affect the IEDG1 bit.
IEDG2 — Input edge 2
This bit determines which level transition on TCAP2 pin will trigger the transfer of the free-running
counter to input capture register 2.
1 (set) – TCAP2 is rising edge sensitive.
0 (clear) – TCAP2 is falling edge sensitive.
When IEDG2 is set, a rising edge on the TCAP2 pin will trigger a transfer of the free-running counter
value to the input capture register. When clear, a falling edge triggers the transfer.
Reset does not affect the IEDG2 bit.
OLVL1 — Output level 1
This bit determines the level that is clocked into the output level register by the next successful
output compare 1 and which will appear on the TCMP1 pin.
1 (set) – A high output level will appear on the TCMP1 pin.
0 (clear) – A low output level will appear on the TCMP1 pin.
When OLVL1 is set, a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level
that will appear on the TCMP1 pin.
MC68HC05L28
16-BIT PROGRAMMABLE TIMER
TPG
MOTOROLA
6-5