MC68HC05L28 Datasheet, PDF (63/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

6.2.2 Timer status register (TSR)
The timer status register ($2E) contains the status bits for the interrupt conditions — ICF, OCF, TOF.
Accessing the timer status register satisfies the first condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
Timer status (TSR)
Address bit 7
$002E IC1F
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
IC2F OC1F TOF TCAP1 TCAP2 OC2F 0 uuuu 11u0
IC1F — Input capture 1 flag
1 (set) – Valid input capture has occurred.
0 (clear) – No input capture has occurred.
This bit is set when the selected polarity of edge is detected by the input capture 1 edge detector;
6
an input capture interrupt will be generated, if IC1IE is set. IC1F is cleared by reading the TSR and
then the input capture low 1 register at $21.
IC2F — Input capture 2 flag
1 (set) – Valid input capture has occurred.
0 (clear) – No input capture has occurred.
This bit is set when the selected polarity of edge is detected by the input capture 2 edge detector;
an input capture interrupt will be generated, if IC2IE is set. IC2F is cleared by reading the TSR and
then the input capture low 2 register at $25.
OC1F — Output compare 1 flag
1 (set) – A valid output compare has occurred.
0 (clear) – No output compare has occurred.
This bit is set when the output compare register contents match those of the free-running counter;
an output compare interrupt will be generated, if OC1IE is set. OC1F is cleared by reading the TSR
and then the output compare low 1 register at $23.
TOF — Timer overflow flag
1 (set) – Timer overflow has occurred.
0 (clear) – No timer overflow has occurred.
This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow
interrupt will occur, if TOIE is set. TOF is cleared by reading the TSR and the counter low register
at $29.
MC68HC05L28
16-BIT PROGRAMMABLE TIMER
TPG
MOTOROLA
6-7