MC68HC05L28 Datasheet, PDF (108/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

Table 10-2 IRQ1 interrupt sensitivity
IRQ1LV
0
0
1
1
IRQ1EDG
0
1
0
1
Interrupt sensitivity
Falling edge
Rising edge
Falling edge and low level
Rising edge and high level
IRQ1RST — IRQ1 reset
The IRQ1 interrupt is cleared by writing a ‘1’ to this bit. This bit is write-only and always returns
zero.
IRQ1VAL — IRQ1 pin status
The IRQ1VAL bit reflects current status of the IRQ1 pin.
IRQ2
Address bit 7
IRQ2 status/control register (IRQ2) $000B
bit 6 bit 5 bit 4 bit 3
bit 2
bit 1
bit 0
State
on reset
IRQ2INT IRQ2ENA IRQ2LV IRQ2EDGIRQ2RSTIRQ2VAL ??00 0000
10
This interrupt can be enabled independently and different sensitivities can be defined: falling edge,
falling edge and low level, rising edge, rising edge and high level. The interrupt is enabled by
setting bit 4 (IRQ2ENA) of register $0B and is disabled by clearing it. The interrupt vector, $3FFA
and $3FFB, s shared with the other IRQ interrupts. Bit 5 of register $0B is an interrupt flag
(IRQ2INT) which distinguishes between the interrupts and is set when an interrupt occurs. The
interrupt is cleared by writing 1 to the IRQ2RST bit which always reads 0. The status of IRQ2 can
be monitored by reading the IRQ2VAL bit (bit 0 on the IRQ2 register).
IRQ2INT — IRQ2 interrupt flag
1 (set) – A valid IRQ2 interrupt has been generated.
0 (clear) – No valid IRQ2 interrupt has been generated.
IRQ2ENA — IRQ2 interrupt enable
1 (set) – IRQ2 interrupts are enabled.
0 (clear) – IRQ2 interrupts are disabled.
IRQ2LV, IRQ2EDG — IRQ2 interrupt sensitivity bits
These two bits are used to select the sensitivity of the IRQ2 interrupt trigger according to
Table 10-2.
MOTOROLA
10-6
RESETS AND INTERRUPTS
TPG
MC68HC05L28