MC68HC05L28 Datasheet, PDF (53/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

5.2
Computer operating properly (COP) watchdog timer
The COP watchdog timer is implemented by dividing the output of the RTI circuit by eight, as
shown in Figure 5-1. The minimum COP timeout period is seven times the RTI period. This is
because the COP will be cleared asynchronously with respect to the value in the core timer
counter register/RTI divider, hence the actual COP timeout period will vary between 7x and 8x the
RTI period. See Table 5-1.
The COP function is enabled by programming the COPON bit in the option register (OPT). See
Section 1.2.1.
If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched.
Writing a ‘0’ to bit 0 of address $0FF0 prevents a COP timeout. When the COP is cleared, only the
final divide-by-eight stage is cleared (see Figure 5-1). See Section 5.3 for register details.
5
Table 5-1 Minimum COP reset times
RT1, RT0
00
01
10
11
Minimum COP reset at bus frequency:
16.384 kHz
7s
4.194 MHz
53.2 ms
f _OP
7 x (RTI rate)
17s
105.7 ms
7 x (RTI rate)
28s
765.8 ms
7 x (RTI rate)
56 s
422.8 ms
7 x (RTI rate)
5.3
Core timer registers
5.3.1 Core timer control and status register (CTCSR)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Core timer control/status (CTCSR) $0008 CTOF RTIF CTOFE RTIE 0
0 RT1 RT0 0000 0011
CTOF — Core timer overflow
1 (set) – The core timer has overflowed.
0 (clear) – The core timer has not overflowed.
This bit is set when the core timer counter register rolls over from $FF to $00; an interrupt request
will be generated if CTOFE is set. When set, the bit may be cleared by writing a ‘0’ to it.
MC68HC05L28
CORE TIMER
TPG
MOTOROLA
5-3