MC68HC05L28 Datasheet, PDF (52/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

As shown in Figure 5-1, the timer is driven by the internal bus clock divided by four with a fixed
prescaler. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be
read by the CPU at any time, by accessing the CTIMER counter register (CTCR) at address $09.
A timer overflow function is implemented on the last stage of this counter, giving a possible
interrupt at the rate of f_OP/1024. The POR signal (t_PORL) is also derived from this register, at
f_OP/4064. The counter register circuit is followed by two more stages, with the resulting clock
(f_OP/16384) driving the real time interrupt circuit. The RTI circuit consists of three divider stages
with a 1-of-4 selector. The output of the RTI circuit is further divided by eight to drive the COP
watchdog timer circuit. The RTI rate selector bits and the RTI and CTOF enable bits and flags are
located in the CTIMER control and status register (CTCSR) at location $08.
CTOF (core timer overflow flag) is a clearable, read-only status bit set when the 8-bit ripple counter
5
rolls over from $FF to $00. A CPU interrupt request will be generated if CTOFE is set. CTOF is
cleared by writing a ‘0’ to it. Writing a ‘1’ has no effect. Reset clears this bit.
When CTOFE (core timer overflow flag enable) is set, a CPU interrupt request is generated when
the CTOF bit is set. Reset clears CTOFE.
The core timer counter register (CTCR) is a read-only register that contains the current value of
the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at f_OP/4 and can
be used for various functions including a software input capture. Extended time periods can be
attained using the CTOF function to increment a temporary RAM storage location simulating a
16-bit (or more) counter.
The power-on cycle clears the entire counter chain and begins clocking the counter. After t_PORL
cycles, the power-on reset circuit is released, which again clears the counter chain and allows the
device to come out of reset. At this point, if RESET is not asserted, the timer starts counting up
from zero and normal device operation begins. When RESET is asserted at any time during
operation (other than POR), the counter chain is cleared. See Section 5.3 for register details.
5.1
Real time interrupts (RTI)
The real time interrupt circuit consists of a three stage divider and a 1-of-4 selector. The clock
frequency that drives the RTI circuit is f_OP/2¹³ (or f_OP/8192), with three additional divider stages,
giving a maximum interrupt period of 4 seconds at a crystal frequency (f_OP) of 32kHz.
The flag (RTIF) is a clearable, read-only status bit which is set when the output of the chosen
(1-of-4 selection) stage becomes active. A CPU interrupt request is generated if RTIE is set. RTIF
is cleared by writing a ‘0’ to it. Writing a ‘1’ has no effect. Reset clears this bit. See Section 5.3 for
register details.
MOTOROLA
5-2
CORE TIMER
TPG
MC68HC05L28