MC68HC05L28 Datasheet, PDF (68/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

6.2.4.2 Output compare register 2
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Output compare high 2 (OCH2) $0026
Unaffected
Output compare low 2 (OCL2) $0027
Unaffected
The 16-bit output compare register 2 is made up of two 8-bit registers at locations $26 (MSB) and
$27 (LSB). The contents of the output compare 2 register are compared with the contents of the
free-running counter once every four internal processor clock cycles. If a match is found, the output
compare 2 flag (OC2F) in the timer status register is set and the output level 2 (OLVL2) bit is
clocked to the TCMP2 pin. The output compare 2 register values and the output level 2 bit should
be changed after each successful comparison to establish a new elapsed timeout. An interrupt can
also accompany a successful output compare provided the corresponding interrupt enable bit
6
(OC2IE) is set.
After a processor write cycle to the output compare register 1 containing the MSB ($26), the output
compare function is inhibited until the LSB ($27) is also written. The user must write both bytes
(locations) if the MSB is written first. A write made only to the LSB will not inhibit the compare
function.
The processor can write to either byte of the output compare 2 register without affecting the other
byte. The output level 2 bit (OLVL2) is clocked to the output level 2 register whether the output
compare 2 flag (OC2F) is set or clear. The minimum time required to update the output compare 2
register is a function of the program rather than the internal hardware. Because the output
compare 2 flag and the output compare 2 register are not defined at power on, and not affected by
reset, care must be taken when initialising output compare functions with software. The following
procedure is recommended:
– write to output compare high 2 to inhibit further compares;
– read the timer status register to clear OC2F (if set);
– write to output compare low 2 to enable the output compare 2 function.
Note:
As the TCMP1 and TCMP2 pins are shared with port D, output compares 1 and 2
cannot be used for compare when the pins are selected to be input. However, the data
register can still be used as a temporary store.
MOTOROLA
6-12
16-BIT PROGRAMMABLE TIMER
TPG
MC68HC05L28