MC68HC05L28 Datasheet, PDF (59/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

6.1
Counter
The key element in the programmable timer is a 16-bit, free-running counter, or counter register,
preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the
timer a resolution of 2µs if the internal bus clock is 2MHz. The counter is incremented during the
low portion of the internal bus clock. Software can read the counter at any time without affecting
its value.
6.1.1
Counter high register
Counter low register
Alternate counter high register
Alternate counter low register
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
6
Timer counter high (TCH)
$0028 (bit 15)
(bit 8) $FF
Timer counter low (TCL)
$0029
$FC
Alternate counter high (ACH) $002A (bit 15)
(bit 8) $FF
Alternate counter low (ACL)
$002B
$FC
The double-byte, free-running counter can be read from either of two locations: the counter register
at $28-$29 or the alternate counter register at $2A-$2B. A read from only the less significant byte
(LSB) of the free-running counter, $29 or $2B, receives the count value at the time of the read. If a
read of the free-running counter or alternate counter register first addresses the more significant byte
(MSB), $28 or $2A, the LSB is transferred to a buffer. This buffer value remains fixed after the first
MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the
free-running counter or alternate counter register LSB and thus completes a read sequence of the
total counter value. In reading either the free-running counter or alternate counter register, if the MSB
is read, the LSB must also be read to complete the sequence.
The alternate counter register differs from the counter register only in that a read of the MSB does
not clear TOF. Therefore the counter alternate register can be read at any time without the
possibility of missing timer overflow interrupts due to clearing of TOF.
If the timer overflow flag (TOF) is set when the counter register LSB is read, then a read of the TSR
will clear the flag.
The free-running counter is set to $FFFC during reset and is always a read-only register. During
a power-on reset, the counter is also preset to $FFFC and begins running after the oscillator
start-up delay. Because the free-running counter is 16 bits preceded by a fixed divide-by-four
prescaler, the value in the free-running counter repeats every 262144 internal bus clock cycles.
TOF is set when the counter overflows (from $FFFF to $0000); this will cause an interrupt if TOIE
is set.
MC68HC05L28
16-BIT PROGRAMMABLE TIMER
TPG
MOTOROLA
6-3