MC68HC05L28 Datasheet, PDF (89/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

MBB — Bus busy
1 (set) – Bus is busy.
0 (clear) – Bus is idle.
This bit indicates the status of the bus. When a START signal is detected, MBB is set. When a
STOP signal is detected, MBB is cleared.
MAL — Arbitration lost
1 (set) – Arbitration lost.
0 (clear) – Default state.
MAL is set by hardware when the arbitration procedure is lost during a master transmission mode.
This bit must be cleared by software.
Bit 3 — Not implemented; always reads zero.
SRW — Read/write command
1 (set) – R/W command bit is set (read).
0 (clear) – R/W command bit is clear (write).
When MAAS is set, the R/W command bit of the calling address sent from a master is latched into
this bit. On checking this bit, the CPU can select slave transmit/receive mode according to the
command of the master.
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MIF — I²C-bus interrupt flag
1 (set) – An I²C-bus interrupt is pending.
0 (clear) – No I²C-bus interrupt is pending.
When this bit is set, an I²C-bus interrupt is generated provided the MIEN bit in the MCR register
is set. MIF is set when one of the following events occurs:
1) The transfer of one byte of data is complete; MIF is set at the falling edge of
the ninth clock after the byte has been received.
2) A calling address is received which matches the address of the I²C-bus in
slave receive mode.
3) Arbitration is lost.
MIF must be cleared by software in the interrupt routine.
RXAK — Received acknowledge bit
1 (set) – No acknowledge signal has been detected at the ninth clock after the
transmission of a byte of data.
0 (clear) – An acknowledge bit has been received at the ninth clock after the
transmission of a byte of data.
MC68HC05L28
I²C-BUS
TPG
MOTOROLA
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