MC68HC05L28 Datasheet, PDF (88/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

MSTA — Master/slave mode select
1 (set) – Master mode; send START signal when set.
0 (clear) – Slave mode; send STOP signal when cleared.
This bit is cleared on reset. When MSTA is changed from 0 to a 1, a START signal is generated on the
bus and the master mode is selected. When this bit changes from a 1 to a 0, a STOP signal is
generated and the slave mode is selected. In master mode, clearing MSTA and then immediately
setting it generates a repeated START signal without generating a STOP signal (see Figure 8-1).
MTX — Transmit/receive mode select
1 (set) – Transmit mode.
0 (clear) – Receive mode.
TXAK — Transmit acknowledge bit
1 (set) – No acknowledge signal response.
0 (clear) – An acknowledge signal will be sent to the bus at the ninth clock bit
after receiving one byte of data.
This bit only has meaning in master receive mode.
8
Bits 2–0 — not implemented; always read zero.
8.4.4
I²C-bus status register (MSR)
I²C-bus status register (MSR)
Address bit 7 bit 6 bit 5 bit 4
$0013 MCF MAAS MBB MAL
bit 3
bit 2
bit 1
bit 0
State
on reset
SRW MIF RXAK 1000 u001
Bits in this register can be read at any time; Bits 4 and 1 can be cleared at any time.
MCF — Data transferring
1 (set) – Data transmit complete.
0 (clear) – Data is being transferred.
MAAS — I²C-bus addressed as a slave
1 (set) – I²C-bus is addressed as a slave.
0 (clear) – I²C-bus is not addressed.
This bit is set when the address of the I²C-bus (specified in MADR) matches the calling address. An
interrupt is generated providing the MIEN bit in the MCR register is set; the CPU then selects its
transmit/receive mode according to the state of the SRW bit. Writing to the MCR register clears this bit.
MOTOROLA
8-8
I²C-BUS
TPG
MC68HC05L28