MC68HC05L28 Datasheet, PDF (64/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

When using the timer overflow function and reading the free-running counter at random times to
measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally
cleared if:
– the timer status register is read or written when TOF is set and
– the LSB of the free-running counter is read, but not for the purpose of
servicing the flag.
Reading the alternate counter register instead of the counter register will avoid this potential
problem.
TCAP1 — Timer capture 1
This bit reflects the current status of the timer capture 1 input.
Note: On the MC68HC05L28, TCAP1 is connected directly to PD0 which defaults to an input
6
with pull-up on reset. TCAP1 will be ‘1’ unless PD0 is externally driven low.
TCAP2 — Timer capture 2
This bit reflects the current state of the timer capture 2 Input.
Note:
On the MC68HC05L28, TCAP2 is connected directly to PD2 which defaults to an input
with pull-up on reset. TCAP2 will be ‘1’ unless PD2 is externally driven low.
OC2F — Output compare 2 flag
1 (set) – A valid output compare has occurred.
0 (clear) – No output compare has occurred.
This bit is set when the output compare register contents match those of the free-running counter;
an output compare interrupt will be generated, if OC2IE is set. OC2F is cleared by reading the TSR
and then the output compare low 2 register at $27.
Bit 0 — always reads zero.
MOTOROLA
6-8
16-BIT PROGRAMMABLE TIMER
TPG
MC68HC05L28