MC68HC05L28 Datasheet, PDF (54/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

RTIF — Real time interrupt flag
1 (set) – A real time interrupt has occurred.
0 (clear) – No real time interrupt has been generated.
This bit is set when the output of the chosen stage becomes active; an interrupt request will be
generated if RTIE is set. When set, the bit may be cleared by writing a ‘0’ to it.
CTOFE — Core timer overflow enable
1 (set) – Core timer overflow interrupt is enabled.
0 (clear) – Core timer overflow interrupt is disabled.
5
Setting this bit enables the core timer overflow interrupt. A CPU interrupt request is generated
when the CTOF bit is set. Clearing this bit disables the core timer overflow interrupt capability.
RTIE — Real time interrupt enable
1 (set) – Real time interrupt is enabled.
0 (clear) – Real time interrupt is disabled.
Setting this bit enables the real time interrupt. A CPU interrupt request is generated when the RTIF
bit is set. Clearing this bit disables the real time interrupt capability.
RT1, RT0 — Real time interrupt rate select
These two bits select one of four taps from the real time interrupt circuitry. Reset sets both RT0
and RT1 to one, selecting the lowest periodic rate and therefore the maximum time in which to alter
them if necessary. The COP reset times are also determined by these two bits. Care should be
taken when altering RT0 and RT1 if a timeout is imminent or the timeout period is uncertain. If the
selected tap is modified during a cycle in which the counter is switching, an RTIF could be missed
or an additional one could be generated. To avoid problems, the COP should be cleared before
changing the RTI taps. SeeTable 5-2 for some example RTI periods.
Table 5-2 Example RTI periods
RT1 RT0
0
0
0
1
1
0
1
1
Division ratio
2¹⁴
2¹⁵
2¹⁶
2¹⁷
Bus frequency
f_OP = 2 MHz
RTI period
Minimum
COP period
8.2ms
57.3ms
16.4ms
114.7ms
32.8ms
229.4ms
65.5ms
458.8ms
MOTOROLA
5-4
CORE TIMER
TPG
MC68HC05L28