MC68HC05L28 Datasheet, PDF (84/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

8.3.3 Data transfer
Once successful slave addressing has been achieved, the data transfer can proceed byte by byte,
in the direction specified by the R/W bit.
Data can be changed only when SCL is low and must be held stable while SCL is high. The MSB
is transmitted first. Each data byte is eight bits long, and there is one clock pulse on SCL for each
data bit. Every byte of data must be followed by an acknowledge bit, which the receiving device
signals by pulling SDA low at the ninth clock. Therefore, one complete data byte transfer needs
nine clock pulses.
If the slave receiver does not acknowledge the master, then the SDA line is left high by the slave.
The master can then generate a STOP signal to abort the data transfer or a START signal to
commence a new calling (called a repeated start).
If the master receiver does not acknowledge the slave transmitter after one byte of transmission,
it means ‘end of data’ to the slave, which then releases the SDA line so that the master can
generate the STOP or START signal.
8.3.4 STOP signal
The master can terminate the communication by generating a STOP signal to free the bus. A
8
STOP signal is defined as a low to high transition of SDA while SCL is high (see Figure 8-1).
8.3.5 Repeated START signal
A repeated START signal generates a START signal without first generating a STOP signal to
terminate the communication. This is used by the master to communicate with another slave, or
with the same slave in a different mode (transmit/receive mode), without releasing the bus.
8.3.6 Arbitration procedure
The I²C-bus is a true multi-master system that allows more than one master to be connected to it.
If two or more masters try to control the bus at the same time, a clock synchronization procedure
determines the bus clock, for which the low period is equal to the longest clock low period and the
high period is equal to the shortest clock high period among the masters. A data arbitration
procedure determines the relative priority of the contending masters; a master loses arbitration if
it transmits logic 1 while another transmits logic 0. The losing masters then immediately switch to
slave receive mode and stop driving SDA outputs. The transition from master to slave mode does
not generate a STOP condition in this case. At this point, the MAL bit in the I²C-bus status register
(MSR) is set by hardware to indicate loss of arbitration.
MOTOROLA
8-4
I²C-BUS
TPG
MC68HC05L28