MC68HC05L28 Datasheet, PDF (65/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

6.2.3 Input capture registers
‘Input capture’ is a technique whereby an external signal (connected to the TCAP1 or TCAP2 pin)
is used to trigger a read of the free-running counter. In this way it is possible to relate the timing of
an external signal to the internal counter value, and hence to elapsed time. There are two identical
input capture registers.
6.2.3.1 Input capture register 1
Input capture high 1 (ICH1)
Input capture low 1 (ICL1)
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0020
Unaffected
$0021
Unaffected
The two 8-bit registers that make up the 16-bit input capture register 1 are read-only, and are used
6
to latch the value of the free-running counter after the corresponding input capture edge detector
senses a valid transition. The level transition that triggers the counter transfer is defined by the
input edge bit (IEDG1). The most significant 8 bits are stored in the input capture high 1 register
at $20 and the least significant in the input capture low 1 register at $21.
An interrupt can accompany a capture if the corresponding interrupt enable bit (IC1IE in timer
control register 1 at $2C) is set.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronisation. Resolution is one count of the free-running counter, which is
four internal bus clock cycles.
The free-running counter contents are transferred to the input capture register on each valid signal
transition whether the input capture 1 flag (IC1F) is set or clear. The input capture register always
contains the free-running counter value that corresponds to the most recent input capture. After a
read of the input capture register MSB ($20), the counter transfer is inhibited until the LSB ($21)
is also read. This causes the time used in the input capture software routine and its interaction with
the main program to determine the minimum pulse period. A read of the input capture register LSB
($21) does not inhibit the free-running counter transfer since the two actions occur on opposite
edges of the internal bus clock.
Reset does not affect the contents of the input capture register, except when exiting STOP mode.
MC68HC05L28
16-BIT PROGRAMMABLE TIMER
TPG
MOTOROLA
6-9