MC68HC05L28 Datasheet, PDF (85/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

8.3.7 Clock synchronization
Since wired-AND logic is performed on the SCL line, a high to low transition on SCL affects all the
devices connected on the bus. The devices start counting their low period and once a device’s
clock has gone low, it holds the SCL line low until the clock high state is reached. However, the
change of low to high in this device clock may not change the state of the SCL line if another device
clock is still within its low period. Therefore, synchronized clock SCL is held low by the device with
the longest low period. Devices with shorter low periods enter a high wait state during this time
(see Figure 8-2). When all devices concerned have counted off their low period, the SCL line is
released and pulled high. There is then no difference between the device clocks and the state of
the SCL line, and all of them start counting their high periods. The first device to complete its high
period pulls the SCL line low again.
SCL1
Start counting high period
Wait
SCL2
Internal counter register
8
SCL
Figure 8-2 Clock synchronization
8.3.8 Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. The slave
device may hold SCL low after the completion of one byte of data transfer (nine bits). In such
cases, it halts the bus clock and forces the master clock into a wait state until the slave releases
the SCL line.
MC68HC05L28
I²C-BUS
TPG
MOTOROLA
8-5