MC68HC05L28 Datasheet, PDF (80/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

7.4
LCD control register
LCD control register (LCD)
Address bit 7 bit 6 bit 5
$001E
VLCDON
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
FDISP MUX4 MUX3 DISON ?000 0000
VLCDON — LCD voltage select
The V_LCD option is not available on the MC68HC05L28 or MC68HC705L28, therefore, this bit must
be cleared.
FDISP — Display frequency
1 (set)
– An extra divide by two stage is included in the LCD clock generator
to give a reduced frame rate. For example, in the 3-way multiplexing
mode, a frame rate of 45.5 Hz instead of 91 Hz can be achieved.
0 (clear) – Default frame rate is used.
MUX4, MUX3 — Multiplex ratio
7
These two bits select the multiplex ratio to be 2, 3 or 4 backplanes.
Table 7-2 Multiplex ratio/backplane selection
MUX4 MUX3 Backplanes Bias Frequency
0
0
2
1/2
61 Hz
0
1
3
1/3
91 Hz
1
0
4
1/3
61 Hz
1
1
2
1/3
61 Hz
DISON — Display ON/OFF
1 (set) – Display is ON.
0 (clear) – Display is OFF
Reserved bits
Bits 4, 5 and 7 are reserved for future use and must be set to 0 when writing to this register.
7.5
LCD during WAIT mode
The LCD does not function during WAIT mode.
MOTOROLA
7-8
LIQUID CRYSTAL DISPLAY DRIVER MODULE
TPG
MC68HC05L28