MC68HC05L28 Datasheet, PDF (75/156 Pages) Motorola, Inc – Flexible general-purpose microcomputer

The operating mode is selected at power on using the multiplex ratio bits (MUX3 and MUX4) in the
LCD control register as shown in Table 7-2.
It is recommended that the DISON bit in the LCD register is not set (display is disabled) until the
multiplex rate is selected. The voltage levels required for the different multiplex rates are generated
internally by a resistive divider chain between V_LCD, V_DD and V_SS.
The 2-way multiplex with 1/3 bias and the three and four-way multiplex options require four voltage
levels, whereas the two-way multiplex with 1/2 bias needs only three levels. Resistors R1, R2 and
R3 are valued at 25kΩ ±40%. Figure 7-2 shows the resistive divider chain network that is used to
produce the various LCD waveforms outlined in Section 7.3.
Note: V_LCD may not exceed the positive power supply voltage V_DD.
Note:
The V_LCD option is not available on the MC68HC05L28 or MC68HC705L28, but is
included here for completeness of the generic module description. Bit 6 of the LCD
control register must be cleared.
Bit 0, $1E
V_LCD
V_DD
7
Bit 6, $1E
2 BP, 1/2 Bias
R3
V2
R2
V1
R1
V_SS
Figure 7-2 Voltage level selection
7.3
Timing signals and LCD voltage waveforms
The LCD timing signals are all derived from the main system clock; with a bus frequency of 2 MHz
(f_osc = 4 MHz) the frame rate will be 61 Hz for 2 and 4-way multiplexing and 91 Hz for 3-way
multiplexing (see Table 7-2). An extra divide-by-two stage can be included in the LCD clock
generator by setting FDISP in the LCD register. This will result in the frame rate being halved. For
MC68HC05L28
LIQUID CRYSTAL DISPLAY DRIVER MODULE
TPG
MOTOROLA
7-3