LAN91C111 Datasheet, PDF (87/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
11.0 BOARD SETUP INFORMATION
The following parameters are obtained from the EEPROM as board setup information:
• ETHERNET INDIVIDUAL ADDRESS
• I/O BASE ADDRESS
• MII INTERFACE
All the above mentioned values are read from the EEPROM upon hardware reset. Except for the INDIVIDUAL
ADDRESS, the value of the IOS switches determines the offset within the EEPROM for these parameters, in such a
way that many identical boards can be plugged into the same system by just changing the IOS jumpers.
In order to support a software utility based installation, even if the EEPROM was never programmed, the EEPROM can
be written using the LAN91C111. One of the IOS combination is associated with a fixed default value for the key param-
eters (I/O BASE) that can always be used regardless of the EEPROM based value being programmed. This value will
be used if all IOS pins are left open or pulled high.
The EEPROM is arranged as a 64 x 16 array. The specific target device is the 9346 1024-bit Serial EEPROM. All
EEPROM accesses are done in words. All EEPROM addresses in the spec are specified as word addresses.
Register
Configuration Register
Base Register
EEPROM Word Address
IOS Value * 4
(IOS Value * 4) + 1
INDIVIDUAL ADDRESS 20-22 hex
If IOS2-IOS0 = 7, only the INDIVIDUAL ADDRESS is read from the EEPROM. Currently assigned values are assumed
for the other registers. These values are default if the EEPROM read operation follows hardware reset.
The EEPROM SELECT bit is used to determine the type of EEPROM operation: a) normal or b) general purpose reg-
ister.
1. NORMAL EEPROM OPERATION - EEPROM SELECT bit = 0
On EEPROM read operations (after reset or after setting RELOAD high) the CONFIGURATION REGISTER and
BASE REGISTER are updated with the EEPROM values at locations defined by the IOS2-0 pins. The INDIVID-
UAL ADDRESS registers are updated with the values stored in the INDIVIDUAL ADDRESS area of the
EEPROM.
On EEPROM write operations (after setting the STORE bit) the values of the CONFIGURATION REGISTER and
BASE REGISTER are written in the EEPROM locations defined by the IOS2-IOS0 pins.
The three least significant bits of the CONTROL REGISTER (EEPROM SELECT, RELOAD and STORE) are
used to control the EEPROM. Their values are not stored nor loaded from the EEPROM.
2. GENERAL PURPOSE REGISTER - EEPROM SELECT bit = 1
On EEPROM read operations (after setting RELOAD high) the EEPROM word address defined by the POINTER
REGISTER 6 least significant bits is read into the GENERAL PURPOSE REGISTER.
On EEPROM write operations (after setting the STORE bit) the value of the GENERAL PURPOSE REGISTER
is written at the EEPROM word address defined by the POINTER REGISTER 6 least significant bits.
RELOAD and STORE are set by the user to initiate read and write operations respectively. Polling the value until
read low is used to determine completion. When an EEPROM access is in progress the STORE and RELOAD
bits of CTR will readback as both bits high. No other bits of the LAN91C111 can be read or written until the
EEPROM operation completes and both bits are clear. This mechanism is also valid for reset initiated reloads.
DS00002276A-page 88
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