LAN91C111 Datasheet, PDF (62/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
8.23 Bank 3 - Management Interface
OFFSET
8
NAME
MANAGEMENT
INTERFACE
TYPE
SYMBOL
READ/WRITE
MGMT
HIGH
BYTE
LOW
BYTE
Reserved
0
MSK_ Reserved Reserved Reserved Reserved Reserved Reserved
CRS100
0
1
1
0
0
1
1
Reserved
MDOE
MCLK
MDI
MDO
0
0
1
1
0
0
MDI Pin
0
MSK_CRS100 - Disables CRS100 detection during transmit in half duplex mode (SWFDUP=0).
MDO - MII Management output. The value of this bit drives the MDO pin.
MDI - MII Management input. The value of the MDI pin is readable using this bit.
MDCLK - MII Management clock. The value of this bit drives the MDCLK pin.
MDOE - MII Management output enable. When high pin MDO is driven, when low pin MDO is tri-stated.
The purpose of this interface, along with the corresponding pins is to implement MII PHY management in software.
8.24 Bank 3 - Revision Register
OFFSET
A
NAME
REVISION REGISTER
TYPE
READ ONLY
SYMBOL
REV
HIGH
BYTE
0
0
1
1
0
0
1
1
LOW
BYTE
CHIP
REV
1
0
0
1
0
0
1
0
CHIP - Chip ID. Can be used by software drivers to identify the device used.
REV - Revision ID. Incremented for each revision of a given device.
DS00002276A-page 62
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