LAN91C111 Datasheet, PDF (36/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
The device can be forced into the Full or Half Duplex modes by either setting the duplex bit in the MI serial port Control
register.
The device can automatically configure itself for Full or Half Duplex modes by using the Auto-Negotiation algorithm to
advertise and detect Full and Half Duplex capabilities to and from a remote terminal. All of this is described in detail in
the Link Integrity and Auto-Negotiation section.
7.7.15.2 10 Mbps
Full Duplex in 10 Mbps mode is identical to the 100 Mbps mode.
7.7.15.3 100/10 Mbps Selection
General
The device can be forced into either the 100 or 10 Mbps mode, or the device also can detect 100 or 10 Mbps capability
from a remote device and automatically place itself in the correct mode.
The device can be forced into either the 100 or 10 Mbps mode by setting the speed select bit in the PHY MI serial port
Control register assuming Auto-Negotiation is not enabled.
The device can automatically configure itself for 100 or 10 Mbps mode by using the Auto-Negotiation algorithm to adver-
tise and detect 100 and 10 Mbps capabilities to and from a remote terminal. All of this is described in detail in the Link
Integrity & Auto-Negotiation section.
7.7.16 LOOPBACK
7.7.16.1 Diagnostic Loopback
A diagnostic loopback mode can also be selected by setting the loopback bit in the MI serial port Control register. When
diagnostic loopback is enabled, transmit data at internal MII is looped back onto receive data output at internal MII, trans-
mit enable signal is looped back onto carrier sense output at internal MII, the TP receive and transmit paths are disabled,
the transmit link pulses are halted, and the Half/Full Duplex modes do not change.
7.7.17 PHY POWERDOWN
The internal PHY of LAN91C111 can be powered down by setting the powerdown bit in the PHY Ml serial port Control
register. In powerdown mode, the TP outputs are in high impedance state, all functions are disabled except the PHY Ml
serial port, and the power consumption is reduced to a minimum. To restore PHY to normal power mode, set the PDN
bit in PHY MI Register 0 to 0. The PHY is then in isolation mode (MII_DIS bit is set); This MII_DIS bit is needed to be
cleared. The device is ready for normal operation 500mS after powerdown is de-asserted.
Note: The PDN bit must not be set when the device is in external PHY mode.
7.7.18 PHY INTERRUPT
The LAN91C111 PHY has interrupt capability. The interrupt is triggered by certain output status bits (also referred to as
interrupt bits) in the serial port. R/LT bits are read bits that latch on transition. R/LT bits are also interrupt bits if they are
not masked out with the Mask register bits. Interrupt bits automatically latch themselves into their register locations and
assert the interrupt indication when they change state. Interrupt bits stay latched until they are read. When interrupt bits
are read, the interrupt indication is deasserted and the interrupt bits that caused the interrupt to happen are updated to
their current value. Each interrupt bit can be individually masked and subsequently be removed as an interrupt bit by
setting the appropriate mask register bits in the Mask register.
lnterrupt indication is done in two ways: (1) MDINT bit in Interrupt Status Register, (2) INT bit in the PHY Ml Serial Port
Status Output register. The INT bit is an active high interrupt register bit that resides in the PHY MI Serial Port Status
Output register.
DS00002276A-page 36
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