LAN91C111 Datasheet, PDF (16/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
7.0 FUNCTIONAL DESCRIPTION
7.1 Clock Generator Block
1. The XTAL1 and XTAL2 pins are to be connected to a 25 MHz crystal.
2. TX25 is an input clock. It will be the nibble rate of the particular PHY connected to the MII (2.5 MHz for a 10 Mbps
PHY, and 25 MHz for a 100 Mbps PHY).
3. RX25 - This is the MII nibble rate receive clock used for sampling received data nibbles and running the receive
state machine. (2.5 MHz for a 10 Mbps PHY, and 25 MHz for a 100 Mbps PHY).
4. LCLK - Bus clock - Used by the BIU for synchronous accesses. Maximum frequency is 50 MHz for VL BUS mode,
and 8.33 MHz for EISA slave DMA.
7.2 CSMA/CD Block
This is a 16 bit oriented block, with fully- independent Transmit and Receive logic. The data path in and out of the block
consists of two 16-bit wide uni-directional FIFOs interfacing the DMA block. The DMA port of the FIFO stores 32 bits to
exploit the 32 bit data path into memory, but the FIFOs themselves are 16 bit wide. The Control Path consists of a set
of registers interfaced to the CPU via the BIU.
7.2.1 DMA BLOCK
This block accesses packet memory on the CSMA/CD’s behalf, fetching transmit data and storing received data. It inter-
faces the CSMA/CD Transmit and Receive FIFOs on one side and the Arbiter block on the other. To increase the band-
width into memory, a 50 MHz clock is used by the DMA block, and the data path is 32 bits wide.
For example, during active reception at 100 Mbps, the CSMA/CD block will write a word into the Receive FIFO every
160ns. The DMA will read the FIFO and accumulate two words on the output port to request a memory cycle from the
Arbiter every 320ns.
The DMA machine is able to support full duplex operation. Independent receive and transmit counters are used. Trans-
mit and receive cycles are alternated when simultaneous receive and transmit accesses are needed.
7.2.2 ARBITER BLOCK
The Arbiter block sequences accesses to packet RAM requested by the BIU and by the DMA blocks. BIU requests rep-
resent pipelined CPU accesses to the Data Register, while DMA requests represent CSMA/CD data movement.
Internal SRAM read accesses are always 32 bit wide, and the Arbiter steers the appropriate byte(s) to the appropriate
lanes as a function of the address.
The CPU Data Path consists of two uni-directional FIFOs mapped at the Data Register location. These FIFOs can be
accessed in any combination of bytes, word, or doublewords. The Arbiter will indicate 'Not Ready' whenever a cycle is
initiated that cannot be satisfied by the present state of the FIFO.
7.3 MMU Block
The Hardware Memory Management Unit allocates memory and transmit and receive packet queues. It also determines
the value of the transmit and receive interrupts as a function of the queues. The page size is 2048 bytes, with a maxi-
mum memory size of 8kbytes. MIR values are interpreted in 2048 byte units.
7.4 BIU Block
The Bus Interface Unit can handle synchronous as well as asynchronous buses; different signals are used for each one.
Transparent latches are added on the address path using rising nADS for latching.
When working with an asynchronous bus like ISA, the read and write operations are controlled by the edges of nRD and
nWR. ARDY is used for notifying the system that it should extend the access cycle. The leading edge of ARDY is gen-
erated by the leading edge of nRD or nWR while the trailing edge of ARDY is controlled by the internal LAN91C111 clock
and, therefore, asynchronous to the bus.
In the synchronous VL Bus type mode, nCYCLE and LCLK are used to for read and write operations. Completion of the
cycle may be determined by using nSRDY. nSRDY is controlled by LCLK and synchronous to the bus.
DS00002276A-page 16
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