LAN91C111 Datasheet, PDF (64/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
9.0 PHY MII REGISTERS
Multiple Register Access
Multiple registers can be accessed on a single PHY Ml serial port access cycle with the multiple register access features.
The multiple register access features can be enabled by setting the multiple register access enables bit in the PHY Ml
serial port Configuration 2 register. When multiple register access is enabled, multiple registers can be accessed on a
single PHY Ml serial port access cycle by setting the register address to 11111 during the first 16 MDC clock cycles.
There is no actual register residing in register address location 11111, so when the register address is then set to 11111,
all eleven registers are accessed on the 176 rising edges of MDC that occur after the first 16 MDC clock cycles of the
PHY Ml serial port access cycle. The registers are accessed in numerical order from 0 to 20. After all 192 MDC clocks
have been completed, all the registers have been read/written, and the serial shift process is halted, data is latched into
the device, and MDIO goes into high impedance state. Another serial shift cycle cannot be initiated until the idle condi-
tion (at least 32 continuous 1's) is detected.
Bit Types
Since the serial port is bi-directional, there are many types of bits. Write bits (W) are inputs during a write cycle and are
high impedance during a read cycle. Read bits (R) are outputs during a read cycle and high impedance during a write
cycle. Read/Write bits (RW) are actually write bits, which can be read out during a read cycle. R/WSC bits are R/W bits
that are self-clearing after a set period of time or after a specific event has completed. R/LL bits are read bits that latch
themselves when they go low, and they stay latched low until read. After they are read, they are reset high. R/LH bits
are the same as R/LL bits except that they latch high. R/LT are read bits that latch themselves whenever they make a
transition or change value, and they stay latched until they are read. After R/LT bits are read, they are updated to their
current value. R/LT bits can also be programmed to assert the interrupt function.
Bit Type Definition:
R:
W:
RW:
R/LT:
Read Only
Write Only
Read/Write
Read/Latch on Transition
R/WSC:
R/LH:
R/LL:
Read/Write Self Clearing
Read/Latch high
Read/Latch low
Register Address
0
1
2,3
4
5
6....15
16
17
18
19
20
Register Name
Control
Status
PHY ID
Auto-Negotiation Advertisement
Auto-Negotiation Remote End Capability
Reserved
Configuration 1
Configuration 2
Status Output
Mask
Reserved
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DS00002276A-page 65