LAN91C111 Datasheet, PDF (35/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
Receive/PHY Control Register is cleared, Auto-Negotiation algorithm is disabled, the selection of 10/100 Mbps mode
and duplex mode is determined by the SPEED bit and the DPLX bit in the MAC Receive/PHY Control register. When
the ANEG bit in the Receive/PHY Control Register is set and the ANEG_EN bit in the MI PHY Register 0 (Control Reg-
ister) is cleared, Auto-Negotiation algorithm is disabled, the selection of 10/100 Mbps mode and duplex mode is deter-
mined by the SPEED bit and the DPLX bit in the MI PHY Register 0 (Control Register).
7.7.12.8 Auto-Negotiation Reset
The Auto-Negotiation algorithm can be initiated at any time by setting the Auto-Negotiation reset bit in the PHY MI serial
port Control register.
7.7.12.9 Link Disable
The link integrity function can be disabled by setting the link disable bit in the PHY Ml serial port Configuration 1 register.
When the link integrity function is disabled, the device is forced into the Link Pass state, configures itself for Half/Full
Duplex based on the value of the duplex bit in the PHY MI serial port Control register, configures itself for 100/10 Mbps
operation based on the values of the speed bit in the Ml serial port Control register, and continues to transmit NLP'S or
TX idle patterns, depending on whether the device is in 10 or 100 Mbps mode.
7.7.13 JABBER
7.7.13.1 100 Mbps
Jabber function is disabled in the 100 Mbps mode.
7.7.13.2 10 Mbps
Jabber condition occurs when the transmit packet exceeds a predetermined length. When jabber is detected, the TP
transmit outputs are forced to the idle state, collision is asserted, and register bits in the PHY Ml serial port Status and
Status Output registers are set.
7.7.13.3 Jabber Disable
The jabber function can be disabled by setting the jabber disable bit in the PHY MI serial port Configuration 2 register.
7.7.14 RECEIVE POLARITY CORRECTION
7.7.14.1 100 Mbps
No polarity detection or correction is needed in 100Mbps mode.
7.7.14.2 10 Mbps
The polarity of the signal on the TP receive input is continuously monitored. If either 3 consecutive link pulses or one
SOI pulse indicates incorrect polarity on the TP receive input, the polarity is internally determined to be incorrect, and a
reverse polarity bit is set in the PHY Ml serial port Status Output register.
The LAN91C111 will automatically correct for the reverse polarity condition provided that the autopolarity feature is not
disabled.
Note: The first 3 received packets must be discarded after the correction of a reverse polarity condition.
7.7.14.3 Autopolarity Disable
The autopolarity feature can be disabled by setting the autopolarity disable bit in the PHY MI serial port Configuration 2
register.
7.7.15 FULL DUPLEX MODE
7.7.15.1 100 Mbps
Full Duplex mode allows transmission and reception to occur simultaneously. When Full Duplex mode is enabled, col-
lision is disabled.
The device can be either forced into Half or Full Duplex mode, or the device can detect either Half or Full Duplex capa-
bility from a remote device and automatically place itself in the correct mode.
 2011-2016 Microchip Technology Inc.
DS00002276A-page 35