LAN91C111 Datasheet, PDF (22/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
FIGURE 7-3:
TX/10BT FRAME FORMAT
INTERFRAME
GAP
PREAMBLE
ETHERNET MAC
FRAME
SFD
DA
SA
LN _{LLC DATA} FCS
INTERFRAME
GAP
IDLE
SSD
PREAMBLE
100 BASE-TX DATA SYMBOLS
SFD
DA
SA
LN _{LLC DATA} FCS ESD _IDLE
IDLE = [ 1 1 1 1...]
SSD = [ 1 1 0 0 0 1 0 0 0 1]
PREAMBLE ^{= [ 1 0 1 0 ...] 62 BITS LONG}
SFD = [ 1 1]
DA, SA, LN, LLC DATA, FCS ^{= [ DATA]}
ESD ^{= [ 0 1 1 0 1 0 0 1 1 1]}
BEFORE / AFTER
4B5B ENCODING,
SCRAMBLING,
AND MLT3
CODING
IDLE
PREAMBLE
10 BASE-T DATA SYMBOLS
SFD
DA
SA
LN LLC DATA FCS SOI
IDLE = [ NO TRANSITIONS]
PREAMBLE _{= [ 1 0 1 0 ... ] 62 BITS LONG}
SFD = [ 1 1]
DA, SA, LN, LLC DATA, FCS = [ DATA]
SOI = [ 1 1 ] WITH NO MID BIT TRANSITION
BEFORE / AFTER
MANCHESTER
ENCODING
IDLE
On the transmit side for 100Mbps TX operation, data is received on the controller and then sent to the 4B5B encoder
for formatting. The encoded data is then sent to the scrambler. The scrambled and encoded data is then sent to the TP
transmitter. The TP transmitter converts the encoded and scrambled data into MLT-3 ternary format, reshapes the out-
put, and drives the twisted pair cable.
On the receive side for 100Mbps TX operation, the twisted pair receiver receives incoming encoded and scrambled MLT-
3 data from the twisted pair cable, remove any high frequency noise, equalizes the input signal to compensate for the
effects of the cable, qualifies the data with a squelch algorithm, and converts the data from MLT-3 coded twisted pair
levels to internal digital levels. The output of the twisted pair receiver then goes to a clock and data recovery block which
recovers a clock from the incoming data, uses the clock to latch in valid data into the device, and converts the data back
to NRZ format. The NRZ data is then unscrambled and decoded by the 4B5B decoder and descrambler, respectively,
and outputted to the Ethernet controller.
10Mbps operation is similar to the 100Mbps TX operation except, (1) there is no scrambler/descrambler, (2) the
encoder/decoder is Manchester instead of 4B5B, (3) the data rate is 10Mbps instead of 100Mbps, and (4) the twisted
pair symbol data is two level Manchester instead of ternary MLT-3.
The Management Interface, (hereafter referred to as the MI serial port), is a two pin bi-directional link through which
configuration inputs can be set and status outputs can be read. Each block plus the operating modes are described in
more detail in the following sections.
7.7.1 MII DISABLE
The internal PHY MII interface can be disabled by setting the MII disable bit in the MI serial port Control register. When
the MII is disabled, the MII inputs are ignored, the MII outputs are placed in high impedance state, and the TP output is
high impedance.
DS00002276A-page 22
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