LAN91C111 Datasheet, PDF (108/125 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

LAN91C111
FIGURE 14-8:
SYNCHRONOUS WRITE CYCLE - NVLBUS=0
Clock
Address, AEN, nBE[3:0]
nADS
W/nR
nCYCLE
Write Data
nSRDY
t10
t9
Valid
t8
t16
t11
t21
t18
t20
t17A
Valid
t21
t8
t9
t10
t11
t16
t17A
t18
t20
t21
Parameter
A1-A15, AEN, nBE[3:0] Setup to nADS Rising
A1-A15, AEN, nBE[3:0] Hold After nADS Rising
nCYCLE Setup to LCLK Rising
nCYCLE Hold after LCLK Rising (Non-Burst Mode)
W/nR Setup to nCYCLE Active
W/nR Hold after LCLK Rising with nSRDY Active
Data Setup to LCLK Rising (Write)
Data Hold from LCLK Rising (Write)
nSRDY Delay from LCLK Rising
MIN
8
5
5
3
0
3
15
4
TYP MAX
Units
ns
ns
ns
ns
ns
ns
ns
ns
7
ns
 2011-2016 Microchip Technology Inc.
DS00002276A-page 109